Goodtwin, on 04 Apr 2013 - 06:12, said:Looks like your right, but the samsung ram is in a x32 organization instead of the x16 I am seeing for Wii U chips.  Did you see a teardown where that chip was used in the Wii U? 


Oh yeah. So far teardowns have found either hybix or samsung. Im pretty sure i posted a pic of tge samsung chip showing the serial number somewhere in this thread.

And the samsung chip being used is the exact same serial number, digit for digit an exact match to the samsung ram used in the 360. Which of course, using anandtech logic of ram chip=which bus, would automatically give the wii u the same bus as the 360. lol.


Ive been using this method for near everything i can find, and its working really well.

360:

128 pins * 1.4Gb/s (or the double pumped clock frequency, the samsung was 700x2) = 179.2gb/s /8 =22.4GB/s.

A direct hit.

I want to do the original wii, but i cant find its clock!!! Or a reliable bandwidth to check against.

Okay. Im guessing the ram in the wii is clocked somewhere in the 2-400mhz range.
IF:
~200MHz 1.9GB/s
~300MHz 2.9GB/s
~400MHz 3.9GB/s


This is fun.

Eh, ive found several hokey claims through google that the wii gddr3 bandwidth is around 4 GB/s. So im leaning towards it being clocked around 400.

oh right. Vegas and nappa, forgot about them. They were embedded ram with about 4GB bw. Probably where those numbers came from.Hokey internet claims rejected.

back to trying to remember. The stupid nomenclature doesnt help. All it brings up with the chip which is that its ranged from like, 200-900MHz....

Eh, ill just guess its 243MHz, like hollywood.

So ~2.4 GB/s for wii ddr3 bandwidth.


Why are so many guests reading this topic all of a sudden?

I would have thought being in a previously 'omg wii u bandwidth is half 360 bandwidth because ram serial numbers despite having the exact same serial number as 360 ram' thread would keep this out of the google attention radar.

You'd think it would.  Demystifying the bandwidth situation is not nearly as interesting to most people as bashing it.

They are saying you are wrong on gaf, with no evidence why!? Strange world!

They aren't reading the thread then or they are just dismissing out of hand.  I've been pouring over whitepapers for the last two days, but they are free to believe what they want.  In the end developers balk at the number Anandtech provided, and in some cases claim that they have numbers better than 360, but they can't go much beyond that in terms of information disclosure.  There are several ways to come to a number, and pretty much every way we've used with the numbers we know gives us a number beyond 12.8.

Also wanted to point out, the chips support bank interleaving and the memory controller should support array interleaving.  Meaning that even with an x16 width, multiple bits within the same chip can be accessed at the same time on different banks, and that addresses can be striped across the chips themselves by the memory controller.

Oh man it's outselling a 7 year old console, hold the presses.

Just like it was big news when PS3 started outselling PS2, which only started happening after they discontinued manufacturing PS2 IIRC.

http://www.samsung.c...c-dram/overview

 

This is what throws a wrench into our theory though.  Notice that they are saying that with the x16 organization, the max bandwidth for the chip is 4.2GB/s, matching up to Anandtech's claim.  They arent saying per bank, but per chip.  It also matches up with PC's and the memory they use.  It would seem strange for graphics cards to have 8 memory chips on the card when four higher density chips could be used.  They are matching up the organization to the memory bus.  If the memory bus is 256 bit, you wont see anything less than 8 memory chips on board.  Eight chips times the x32 organization gives us the 256bit bus.  

 

Keep in mind that the Xbox 360 uses 8 seperate chips while the WIi U only has 4.  

Bit density in DDR3 should not effect bus width.

What we have are four modules, each is organized thusly, 256(rows)x16(columns)x8(banks).  This dictates how the memory is organized within the array itself, but the bus width per chip on a standard DDR3 interface is 32bit, or at least should be.

Didn't Hynix themselves confirm that each housing could support a 32 bit bus?

Goodtwin, on 04 Apr 2013 - 04:59, said:http://www.samsung.c...c-dram/overview
This is what throws a wrench into our theory though.  Notice that they are saying that with the x16 organization, the max bandwidth for the chip is 4.2GB/s, matching up to Anandtech's claim.  They arent saying per bank, but per chip.  It also matches up with PC's and the memory they use.  It would seem strange for graphics cards to have 8 memory chips on the card when four higher density chips could be used.  They are matching up the organization to the memory bus.  If the memory bus is 256 bit, you wont see anything less than 8 memory chips on board.  Eight chips times the x32 organization gives us the 256bit bus.  
Keep in mind that the Xbox 360 uses 8 seperate chips while the WIi U only has 4.  



Were gravy dude.

Right, 360 only had four chips as well.  I still think that using the pin counts inside the GPU are going to be the best measure of the bus width.

Actually we have the answer to that.

256.

Found it when i found out the 360 uses the same ram chip as the wii u's samsung ram.

Samsung k4j52324qc-bc14

macroware.wordpress.com/2006/01/24/whats-inside-the-microsoft-xbox-360/

though the 360 only uses half the pins.

We dont know the pins on the ram side, but we know the pins where they plug in. 158 pins on the ddr3 io

1.6 * 158=252.8/8=31.6

31.6 GB/s

Its looking pretty rock solid.

Yeah, that lines up way too perfectly.  1.6 per pin, 158 pins.  We're golden.

Yep, 15 i think too. City is fun exploring, I could spend hours just messing around 

I kept getting sidetracked yesterday on the way to the missions, any time I saw a blue and white ledge or something I had to stop and see where it lead.

I don't get it.
It'll be like $5 next sale for PC, meanwhile it'll remain like 60 on wii u for years.

They're upset over the boss fight improvements.  Which is natural for a remake to have enhancements.  I don't get it either.  I have the game for PC and it was brilliant, there isn't any need for this whining.

Yeah, lots of angst from the PC crowd.  Shame I'm actually part of that community

I'm sure Dragon Quest had something to do with it but there is no way a game like Game & Wario would spike hardware sales.

G&W is #10 this week on Japanese sales charts

i have a huge image file of it, 9mbsize,  I can zoom in and make 1 pin a huge image... so I counted them very easy...

An odd overall number of pins for two DDR3 channels would be very... ahem, odd.

I really like the idea of a Rally game that has an option for a navigator.

Oh no, I meant Crytek could have made something on the PS3 that looks better than what EPIC did on this PS4 demo. Basically im just saying im not seeing the cause for any ps4 hype because the graphics so far just look like what a respectable developer like Crytek has already done with ps3.

Ahhhh, yeah they probably could have. 

The press conferences have never been open access as you call it. Yes the show floor has been accessible to the general public at Gamescom and Tokyo game show but that's not the same thing. E3 is trade only and has always been that way. Sure some people like me do get in even though we are not supposed to. It's only with the advent of press conferences being streamed on the Internet that the general public has got so much exposure to what's hapenning in the games industry.


Whether that's true or not the majority of the audience is trade only and it's always been that way. I've attended several of the press conferences in the past both at E3 and Gamescom.

Noted

Nintendo's E3 showing will probably be incredible this year, if it's not then they might struggle for a while depending on the PS4's showing.

Its getting close, they need to start blowing the horn on the hype train.  I think We'll see a direct for Wii U in April, alongside the patch release.  Hopefully one or two decent announcements.

Im really not moved at all by the ps4 yet, I would really hope those framerates are cleaned up for the amount of hype and bold statements like "ps4 will outperform most pc's". Honestly Crytek could of pulled off that PS4 demo on the PS3....

You mean EPIC?  They could have pulled off most of it, at least made it look similar, hell they could make it look the same in UE3.

For god same man it hasn't even been a year.

Seriously, its only been 4 months and there are people here jumping on hare trains, threatening to sell their consoles, and generally getting angry and for what?  There are games to play, if none of them suit you, wait until some do, or switch do a different platform while you wait for the games you are waiting for.

Take a look at the chest plate armor on the fire dude. Texture reflections on pc. Completely absent on ps4.

If ue4 belongs on ps4 then it definitely belongs on wii u.

It's fine to port an engine, so you can take advantage of a few new features and an updated and streamlined workflow, but honestly both the Wii U and PS4 have near featureset parity.

I counted 155

 

Horizontal 79

vertical 76

There are 79 there, 3 of them are darker than the rest, I counted the leads rather than the pins themselves because they're easy to miss.

Really? Like 4th in all video game department sales?

I think it was just 4th on VGChartz pro, which has weekly numbers.

Yeah, nothing.  The first game was very cool when I was in middle school, GTA 2 was even pretty cool.  I was able to play GTA3 off and on, then I kinda got over it and wasn't able to enjoy it anymore.

It just makes sense all round. 

 

It always seemed rather unlikely that games like Sonic & All-Stars Racing Transformed could basically be the same game as running on PS360 but with better textures, if it didn't have increased RAM bandwidth to actually access those higher resolution textures.  The more detailed the textures, the more memory bandwidth you need.  Upon switching from the Wii U version to the Xbox 360 one, I'm sure I noticed a reduction in graphical effects on a few levels too.  Although I found the frame rate more constant on Xbox 360, likely down to the fact the game really was launched on too many platforms and as the Wii U was the easiest to hit the target frame rate, it seems they slacked off on a few sections where it takes a real nose dive (eg the NiGHTS level).

 

Then there is LEGO City Undercover which a lot of people seem to be complaining doesn't look impressive graphically.  I admit, my first impression was really bad, the frame rate was so low it initially gave me a headache and I had to enable the frame-doubling on my TV to compensate (but it adds horrible latency).  Over time I adjusted to it and started to appreciate some of its charm, especially as a first-gen title.

 

The texture work in particular is superb, not a single blocky texture in the whole game that I saw.  I'm fairly convinced its using tessellation as the hills and banks are really smooth compared to PS360.  Of course it has some bugs too and the draw distance/depth of field effect is something I hate.  But it certainly shows off things I just do not see could have been possible without greater memory bandwidth.

Well said, and I'm just about to jump back into Lego City.

routerbad, on 03 Apr 2013 - 09:46, said:The fact that it's DDR3 should have debunked it right away.  They applied a 16 bit width per chip which isn't the case in a dual die package.  They should have assumed 32 bit per chip or count the lanes, which is normal for graphics applications.

I'm good with that.  What's going into the GPU is going to tell the whole story with regard to the bus width.



I think i remember starting to go down that path. Then i got distracted by something and forgot what why i was doing it XD.

Whelp,i am pretty confident in this bandwidth. It was a bit of a weird layout, but thats nintendo for you.

Mystery solved gentlemen?

Solved.  Anandtech analysis debunked.

If anything wouldnt the GPU having so many pins/lanes debunk the idea of 16bit right away?  The GPU is custom, so there would be no point in having more memory lanes at the GPU than required. 

The fact that it's DDR3 should have debunked it right away.  They applied a 16 bit width per chip which isn't the case in a dual die package.  They should have assumed 32 bit per chip or count the lanes, which is normal for graphics applications.

Goodtwin, on 03 Apr 2013 - 09:11, said:If anything wouldnt the GPU having so many pins/lanes debunk the idea of 16bit right away?  The GPU is custom, so there would be no point in having more memory lanes at the GPU than required. 



------------------------
Exactly.


routerbad, on 03 Apr 2013 - 09:07, said:Just did another count, 158 pins.  79 per side.  Unless I'm counting some of them wrong, a few of them are hard to make out.


That gddr3 64bit card has 63 pins.

I think weve had a breakthrough. I thought those lanes were abnormally large.

158 pins... 158 bit bus????

(fixed, lmao)

800x2x158=252,800/8=31,600

31.6GB/s?

I'm good with that.  What's going into the GPU is going to tell the whole story with regard to the bus width.

Interesting, maybe we're missing 1 pin per channel here.

Apparently the hynix model used is DDR3 "graphics memory"  Same specs list though.

Those pins on the gpu gddr3 io.... they should be 1 for 1 with the bits of the bus....



typical 64 bit gddr3 1GB ram card. 4 ram chips (removed you can see the grid ball array)



16 lanes per chip, adding up to 64 bit bus. Normal.

They go through the card, and are condensed into 16 thicker lanes, these lanes make their way back to the memory sockets,and are split back up to 64 pins, in 3,4 pin groups to be plugged into the mother board.

are our 88 lanes being split up to a 160 something pin layout on the gpu?
 

usually consoles lanes are wired like the individual ram chips, and not grouped like the traces leading to the pins....

I NEED to see how the ram connects to the gpu.

Just did another count, 158 pins.  79 per side.  Unless I'm counting some of them wrong, a few of them are hard to make out.

routerbad, on 03 Apr 2013 - 08:28, said:I think I may have gone overboard there, it wouldn't be an 88bit channel per chip, it would be 22 (44 per chip in dual channel mode) which would make the total bus 176.
If we go by that we have 800*2(data rate)*2(interfaces, or dual channel)*88 (bus width)/8 = 35,200Mb/s  I think that is the most reasonable number, and one you provided earlier.
Another way to look at it is 200*2*4*88/8 for 17.6 then double that for dual channel for the same number.


That makes my gut happy.

But these lanes... Somethins not right. Is their a memory controller inside those ram housings?

Yeah 12.8 wasn't sitting well with me either.

routerbad, on 03 Apr 2013 - 07:49, said:Aha, it would be 
Ahh, it would be 17.6 PER MODULE though, each module is on a separate 88 bit channel width.
Funny thing, 17.4 * 4 modules is 69.6, which isn't far off from what we've been saying.


----------------------------------
across 11 lanes per chip.... hmmmm.... I want to see the underside of the wii u motherboard.

routerbad, on 03 Apr 2013 - 07:49, said:Aha, it would be 
Ahh, it would be 17.6 PER MODULE though, each module is on a separate 88 bit channel width.
Funny thing, 17.6 * 4 modules is 70.4, which isn't far off from what we've been saying.
Basically the 800MHz number we are using for the memory clock rate rather than 200MHz is effectively giving us the same number based on four chips.  So I think goodtwins was correct with using 200MHz as the memory clock rate (though strangely the Micron website lists it as an 800MHz memory clock, not IO clock).  Going by that, we have:
200*2*4*88/8=17,600Mb/s * 4 Modules = 70,400Mb/s  exact same number 


Yeah, the memory clock was doing me in the head too. I wonder if one of the other ram suppliers is correctly listed.

----------------------------------------------
ah the underside of the wii u motherboard.

http://guide-images....VPDtCY6ppv.huge

I think I may have gone overboard there, it wouldn't be an 88bit channel per chip, it would be 22 (44 per chip in dual channel mode) which would make the total bus 176.

If we go by that we have 800*2(data rate)*2(interfaces, or dual channel)*88 (bus width)/8 = 35,200Mb/s  I think that is the most reasonable number, and one you provided earlier.

Another way to look at it is 200*2*4*88/8 for 17.6 then double that for dual channel for the same number.