But looking at charts for DDR3-1600 the memory clock is actually 200mhz, with the bus clock being 800Mhz, and then double data gives the 1600. So they are already giving you the 4x multiplier when you read the 800Mhz.
Aha, it would be
routerbad, on 03 Apr 2013 - 07:07, said:Yep, full duplex interface as well.
80 per edge it looks like, though I may be off a little (between 2-6 pins more perhaps) Looks like there are 4 clusters of 11 pins, and supporting pins in between, possibly for CPU I/O to give the CPU access to Mem2
That is on each side.
Thats pretty much what i got, though it was hard on my eyes, so i thought i may have been off.
Okay, I know something isnt right. So im going to stick with goodtwins 17.6GB/s from the wiki formula and add bandwidth per feature until the bug is ironed out, im just happy 12.8 is 100% busted.
So, those clusters of 11 pins make sense.
44 on each side gives us 88.
Ahh, it would be 17.6 PER MODULE though, each module is on a separate 88 bit channel width.
Funny thing, 17.6 * 4 modules is 70.4, which isn't far off from what we've been saying.
Basically the 800MHz number we are using for the memory clock rate rather than 200MHz is effectively giving us the same number based on four chips. So I think goodtwins was correct with using 200MHz as the memory clock rate (though strangely the Micron website lists it as an 800MHz memory clock, not IO clock). Going by that, we have:
200*2*4*88/8=17,600Mb/s * 4 Modules = 70,400Mb/s exact same number ![]()


