270 replies to this topic

[Goodtwin]

DDR3-1600 is quad pumped seeing as how the internal memory is clocked at 200Mhz, quad pumped gets us to the 800Mhz, then the double data gets us to the 1600.  There are no futher multipliers, we did all those to get to the 1600.  You cant keep adding multipliers, they are already calculated in the DDR3-1600.  200Mhz x 4(quad pumped) x 2(double data) x 16 (data width)=25,600 bits or 3.2GB/s per chip.  

 

This lines up 100% with what Hynix is saying, 1600Mb per pin.  I can have 2 lanes merge into a 4 lane highway, the limiting factor is the two lane highway.  Hynix is saying that the maximum data transfer rate is 1600Mb/s, that already accounts for double data and quad pumped. 

[routerbad]

DDR3-1600 is quad pumped seeing as how the internal memory is clocked at 200Mhz, quad pumped gets us to the 800Mhz, then the double data gets us to the 1600.  There are no futher multipliers, we did all those to get to the 1600.  You cant keep adding multipliers, they are already calculated in the DDR3-1600.  200Mhz x 4(quad pumped) x 2(double data) x 16 (data width)=25,600 bits or 3.2GB/s per chip.  

 

This lines up 100% with what Hynix is saying, 1600Mb per pin.  I can have 2 lanes merge into a 4 lane highway, the limiting factor is the two lane highway.  Hynix is saying that the maximum data transfer rate is 1600Mb/s, that already accounts for double data and quad pumped. 

You are swapping between mem clock and bus clock references.  The memory clock is actually 800MHz or 900MHz for DDR3 irrespective of the bus itself.

[Goodtwin]

You are swapping between mem clock and bus clock references.  The memory clock is actually 800MHz or 900MHz for DDR3 irrespective of the bus itself.

 

No is isnt.  Internal memory clock speed is 200Mhz. 

[3Dude]

double pumping doesnt actually have anything to do with the clock.

What you are talking about is the 'effective clock speed'. Its actually a marketing phrase/shortcut.

However you can only use it if you have every peice of information in its proper place.

You get that effective speed when you double the data per lane per clock.

Its not the clock rate that really doubles, its the data per clock per lane. But because that didnt market well, they came up with 'effective clock speed'.

Our problem is, the system bus and its lanes, and the 2 bits per lane per clock they get, arent being taken into consideration.

[routerbad]

No is isnt.  Internal memory clock speed is 200Mhz. 

Core memory speed, yes.  But the quadrupling of performance compared to DDR is based on the quadrupled prefetch, and that is the big difference between DDR, DDR2, and DDR3 components at the silicon level.  A wider prefetch.  All of the other changes are at the bus, but are based on the expanded prefetch.

 

800MHz is the clock that the memory itself is rated at, not because it is quad pumped, but because of the 200MHz array frequency and the 4X larger prefetch over DDR.

[Goodtwin]

I understand that, my math is right guys.  I dont know what to tell you about the lanes, but Hynix gave us the bandwidth per pin and the number of pins. 

[routerbad]

I understand that, my math is right guys.  I dont know what to tell you about the lanes, but Hynix gave us the bandwidth per pin and the number of pins. 

And yet there are more lanes connected to each chip than should be possible.  They aren't connected to nothing, and DDR3 doesn't support on chip ECC, it makes absolutely zero sense to have the amount of lanes on the motherboard that there are or the amount of IO on the GPU that there is if that was the limiting factor.  

[3Dude]

I understand that, my math is right guys. I dont know what to tell you about the lanes, but Hynix gave us the bandwidth per pin and the number of pins.

I know man. It just doesnt add up, and there are a lot of possible reasons we have to start eliminating.

Hell, the housing could be mismatched with the components. Its happened before, particular with large shipments under a hard time line.

When they gave you the data rate per pin, did they mention that that data rate as ddr would or would not go through twice per clock (once for rise and once for fall)?

Edited by 3Dude, 08 April 2013 - 11:21 AM.

[Goodtwin]

I gave you what they said, maximum bandwidth per pin is 1600Mb.

 

http://www.ps3devwiki.com/wiki/RAM

 

If you look at the the way the PS3 graphics memory bandwidth is calculated, its the very same way everyone has calculated the the Wii U ram bandwidth.

 

700Mhz x 2 (double data) x 32 (data organization) x 4chips= 22.4GB/s.

[3Dude]

I gave you what they said, maximum bandwidth per pin is 1600Mb.

http://www.ps3devwiki.com/wiki/RAM

If you look at the the way the PS3 graphics memory bandwidth is calculated, its the very same way everyone has calculated the the Wii U ram bandwidth.

700Mhz x 2 (double data) x 32 (data organization) x 4chips= 22.4GB/s.

The physical bus matches the data bus used in the 'effective clock rate' shortcut.

These are 2 different situations. That shortcut doesnt work here, be ause of the bus difference.

Also, 1600mb per pin, assuming the chips arent mis labeled, accounting for 2 bits per pin per clock, would get you 3200mb per clock, at different moments, while never technically exceeding 1600mb per pin.

Its why im asking if he mentioned it specifically or not.

Edited by 3Dude, 08 April 2013 - 11:46 AM.

[Goodtwin]

http://download.micr...f16c256x64h.pdf

 

This shows that the only way to get maximum bandwidth from a single DDR3 module is to have 64 pins, the Wii U modules have 16 pins. 

 

We could have 20 pins connected in series, the 10 lanes that connect the chips, then with 12 pins connected independently. 

 

As for the chips being misslabeled, I wouldnt discredit that if we didnt have two different manufactures ram with the same specs.  Both Hynix and Samsung have the same specs.   

[routerbad]

http://download.micr...f16c256x64h.pdf

 

This shows that the only way to get maximum bandwidth from a single DDR3 module is to have 64 pins, the Wii U modules have 16 pins. 

 

We could have 20 pins connected in series, the 10 lanes that connect the chips, then with 12 pins connected independently. 

 

As for the chips being misslabeled, I wouldnt discredit that if we didnt have two different manufactures ram with the same specs.  Both Hynix and Samsung have the same specs.   

What that paper refers to as module, and what you are referring to as module are two separate things.  They refer to each individual chip as a "component" and a module refers to a DIMM.

 

This is also a completely different situation, and actual results will always vary with custom embedded RAM vs PC centric DIMMs.  The components themselves are the same, but the delivery method is different.

Edited by routerbad, 08 April 2013 - 12:11 PM.

[3Dude]

Goodtwin, on 08 Apr 2013 - 06:04, said:http://download.micr...f16c256x64h.pdf
This shows that the only way to get maximum bandwidth from a single DDR3 module is to have 64 pins, the Wii U modules have 16 pins.
We could have 20 pins connected in series, the 10 lanes that connect the chips, then with 12 pins connected independently.
As for the chips being misslabeled, I wouldnt discredit that if we didnt have two different manufactures ram with the same specs. Both Hynix and Samsung have the same specs.


We actually have more than samsung and hynix with the same specifications making a mislabel even more remote.

Im pretty sure I went over a micron too.

Edited by 3Dude, 08 April 2013 - 12:17 PM.

[routerbad]

Goodtwin, on 08 Apr 2013 - 06:04, said:http://download.micr...f16c256x64h.pdf
This shows that the only way to get maximum bandwidth from a single DDR3 module is to have 64 pins, the Wii U modules have 16 pins.
We could have 20 pins connected in series, the 10 lanes that connect the chips, then with 12 pins connected independently.
As for the chips being misslabeled, I wouldnt discredit that if we didnt have two different manufactures ram with the same specs. Both Hynix and Samsung have the same specs.


We actually have more than samsung and hynix with the same specifications making a mislabel even more remote.

Im pretty sure I went over a micron too.

Yep

[Goodtwin]

Goodtwin, on 08 Apr 2013 - 06:04, said:http://download.micr...f16c256x64h.pdf
This shows that the only way to get maximum bandwidth from a single DDR3 module is to have 64 pins, the Wii U modules have 16 pins.
We could have 20 pins connected in series, the 10 lanes that connect the chips, then with 12 pins connected independently.
As for the chips being misslabeled, I wouldnt discredit that if we didnt have two different manufactures ram with the same specs. Both Hynix and Samsung have the same specs.


We actually have more than samsung and hynix with the same specifications making a mislabel even more remote.

Im pretty sure I went over a micron too.

 

Yea, I have seen the Micron specs as well, and they all point to a 16 pin design. 

 

I do have to ask, why are you guys so sure the 12.8GB/s is wrong?  Specifically, if the Wii U does write to the edram and not the main memory, that means the Wii U has 12.8GB/s for reading from the main memory, more than the 360.  There are graphics cards with the same bandwidth AMD HD5450 that have 12.8GB/s of memory bandwidth that are able to run current gen games.  And they have to share that memory for read and writes. 

 

[routerbad]

Yea, I have seen the Micron specs as well, and they all point to a 16 pin design. 

 

I do have to ask, why are you guys so sure the 12.8GB/s is wrong?  Specifically, if the Wii U does write to the edram and not the main memory, that means the Wii U has 12.8GB/s for reading from the main memory, more than the 360.  There are graphics cards with the same bandwidth AMD HD5450 that have 12.8GB/s of memory bandwidth that are able to run current gen games.  And they have to share that memory for read and writes. 

 

12.8 is not very good for graphics memory.  They would have serious issues porting 360 games if that was the case, and the 360 had a higher read throughput than that, 22.4GB/s through the main memory bus, and 256GB/s between main ram and edram.  Would the bandwidth between edram and DDR3 be higher on the Wii U as well?  This I don't know much about.

 

That would actually make sense with regard to your comment, because if the bus speed is that fast between edram and main, only reads would be performed from main RAM, and all writes could go to edram and edram could shift data in and out at super high speed.  It would actually be competitive in comparison to GDDR5 at that point, because the effective throughput would be much, much higher than 12.8GB/s.  

Edited by routerbad, 08 April 2013 - 12:49 PM.

[3Dude]

Goodtwin, on 08 Apr 2013 - 06:50, said:Yea, I have seen the Micron specs as well, and they all point to a 16 pin design. 
I do have to ask, why are you guys so sure the 12.8GB/s is wrong?  Specifically, if the Wii U does write to the edram and not the main memory, that means the Wii U has 12.8GB/s for reading from the main memory, more than the 360.  There are graphics cards with the same bandwidth AMD HD5450 that have 12.8GB/s of memory bandwidth that are able to run current gen games.  And they have to share that memory for read and writes. 




Mainly because nfsmw-u would be impossible with the same number of textures at much higher resolutions.... as a 360 port.

They could be stored in the 32MB edram while the level is loading, but whenever anything needed to be swapped out in game, the game would be forced to swap from main at a game halting 12.8 GB/s vs 22.4 GB/s. But not only does it not stutter when streaming from main, it performs better than either ps3 or 360. Unless the ps360 only use a fraction of their bandwidth, something fishy.

Then adding too, the ram bus is just too big to be a 16 bit per chip ddr3 bus.

Somethings not right. Why is the bus so big?

Also, what settings is that pc ver. of the game on? it looks..... bad.

Edited by 3Dude, 08 April 2013 - 01:07 PM.

[Goodtwin]

Yea, the bandwidth to the edram on the Wii U would be higher.  The 360's edram wasnt really edram on the first versions of the 360, it was on a seperate chip that was placed onto the 360.  You sure about the 360 bandwidth, I read that it was cut in half for reads and writes.  Like I pointe out, a HD5450 can run Need For Speed Most Wanted and has only 12.8GB/s of bandwidth.  The bandwidth savings from edram is huge, so the Wii U would be in far better shape even with only 12.8GB/s to the main memory pool.  The edram is the performer here.  Its fast, and has enough capacity to hold the bandwidth hogs allowing the main memory to be used exclusively for reads.  Keep in mind that the 360 always has to send the framebuffer to the main memory before it can be sent out of display.  It also has to use tiling to do a 720p frame with AA, eating up even more bandwidth to the main memory.   

[routerbad]

Goodtwin, on 08 Apr 2013 - 06:50, said:Yea, I have seen the Micron specs as well, and they all point to a 16 pin design. 
I do have to ask, why are you guys so sure the 12.8GB/s is wrong?  Specifically, if the Wii U does write to the edram and not the main memory, that means the Wii U has 12.8GB/s for reading from the main memory, more than the 360.  There are graphics cards with the same bandwidth AMD HD5450 that have 12.8GB/s of memory bandwidth that are able to run current gen games.  And they have to share that memory for read and writes. 




Mainly because nfsmw-u would be impossible with the same number of textures at much higher resolutions.

They could be stored in the 32MB edram while the level is loading, but whenever anything needed to be swapped out in game, the game would be forced to swap from main at a game halting 12.8 GB/s vs 22.4 GB/s. But not only does it not stutter when streaming from main, it performs better than either ps3 or 360.

Then adding too, the ram bus is just too big to be a 16 bit per chip ddr3 bus.

Somethings not right. Why is the bus so big?

Exactly what I'm wondering.

[3Dude]

Goodtwin, on 08 Apr 2013 - 07:10, said:Yea, the bandwidth to the edram on the Wii U would be higher.  The 360's edram wasnt really edram on the first versions of the 360, it was on a seperate chip that was placed onto the 360.  You sure about the 360 bandwidth, I read that it was cut in half for reads and writes.  Like I pointe out, a HD5450 can run Need For Speed Most Wanted and has only 12.8GB/s of bandwidth.  The bandwidth savings from edram is huge, so the Wii U would be in far better shape even with only 12.8GB/s to the main memory pool.  The edram is the performer here.  Its fast, and has enough capacity to hold the bandwidth hogs allowing the main memory to be used exclusively for reads.  Keep in mind that the 360 always has to send the framebuffer to the main memory before it can be sent out of display.  It also has to use tiling to do a 720p frame with AA, eating up even more bandwidth to the main memory.   


Well, yes that gpu is running it, but it doesnt look near as good in many aspects, i wont comment on frame rate cause of youtube, but the pop in is atrocious.

here is the 360 memory diagram.



Now, im not actually concerned with writes, i know we got it beat to a pulp with the edram. And imaware it frees up bandwidth.

Im concerned with reads from main, streaming in assets. It appears most places i look, the 360 gets the full 22.4 GB/s for reads. if it doesnt, well, then the wii u doesnt have half the bandwidth.

And of course, again, ive still got this big ol fat bus just staring at me.

Why is the bus from the ddr3 so big?

Edited by 3Dude, 08 April 2013 - 01:20 PM.