270 replies to this topic

[3Dude]

Goodtwin, on 02 Apr 2013 - 05:30, said:Thats what I did.  Their spec sheet says the chip is a 96ball chip, I cant find good info on what that means.  Is that where the data is transfered? 


nah man, thats what they use to bolt the sucker on. Sounds fancy though right? Grid ball array? XD

http://en.wikipedia....Ball_grid_array

Edited by 3Dude, 02 April 2013 - 11:38 AM.

[routerbad]

Goodtwin, on 02 Apr 2013 - 05:30, said:Thats what I did.  Their spec sheet says the chip is a 96ball chip, I cant find good info on what that means.  Is that where the data is transfered? 


nah man, thats what they use to bolt the sucker on. Sounds fancy though right? Grid ball array? XD

http://en.wikipedia....Ball_grid_array

Yep, just a mounting method.  Pin Grid Array and Land Grid Array being the less permanent types.

[Goodtwin]

Ok, so 32bit is the maximum bus for ram modules.  I was assuming that it would be higher since there are high bandwidth memories like GDDR5, but apprently they get the bandwidth by having lots and lots of ram modules on the memory bus, and they run at way higher speeds than DDR3.  So if a graphics card for example has a 256bit memory bus, it would have to have eight 32bit ram modules to get maximum bandwidth.  If they were to use 16bit ram modules on that same graphics card, then there would have to be 16 ram modules on that memory bus.  I had to go look at some PC GPU's to see how in the world they were getting all that bandwidth.  Even when looking at GDDR5 memory on Hynix website, your going to notice that the bandwidth per brick of ram isnt that impressive, which was strange to me at first, but then I realized that bandwidth is simply a result of having lots of ram chips.  So having more low density ram modules instead of fewer high density ram modules is actually beneficial for bandwidth. 

[3Dude]

Goodtwin, on 02 Apr 2013 - 06:47, said:Ok, so 32bit is the maximum bus for ram modules.  I was assuming that it would be higher since there are high bandwidth memories like GDDR5, but apprently they get the bandwidth by having lots and lots of ram modules on the memory bus, and they run at way higher speeds than DDR3.  So if a graphics card for example has a 256bit memory bus, it would have to have eight 32bit ram modules to get maximum bandwidth.  If they were to use 16bit ram modules on that same graphics card, then there would have to be 16 ram modules on that memory bus.  I had to go look at some PC GPU's to see how in the world they were getting all that bandwidth.  Even when looking at GDDR5 memory on Hynix website, your going to notice that the bandwidth per brick of ram isnt that impressive, which was strange to me at first, but then I realized that bandwidth is simply a result of having lots of ram chips.  So having more low density ram modules instead of fewer high density ram modules is actually beneficial for bandwidth. 

Yes. Thats what the channesl mean. a 64 bit bus has 2 channels in that case. For 'natural' 64 bit busses, its just as simple, more lanes connect to the different modules inside the chip. Its called a double wide, but its just 2 32 bit busses. After all, all ram chips are made of smaller modules under 1 housing. wii u has a 128 bit bus, in this case. with half sent to games and half to system.

Interleaving helps reduce some of the clutter, but its not always practical, the 360 didnt use it because it was just too hot already, so the ram only had half the bandwidth for the number of modules it had.

there are 4 modules for each ram chip pair on the wii u.

with 2 channels we have a 64 bit bus, technically a 128 bit bus, but half is cut off.

anand tech said all 4 added up to 1 64 bit bus.

If you are saying hynix says 32bit per brick (standard for ddr3 2 channel, 64 bit), we are looking at a doubling of the bandwidth from anandtech.

Notice how the pairs of ram are connected by bus lanes to the back ends?

actually, reminds me of the ps4 ram. That also had 'paired' pools.



Huh. only 8 lines per chip. Wii u has 3 more lanes per chip on its bus.

eh, for some reason the wii u pic disappeared.



it has 11 lanes to its bus per chip vs ps3's 8.

Edited by 3Dude, 02 April 2013 - 01:41 PM.

[routerbad]

Just looked again at the Wii U motherboard.  The way the RAM bus lanes go into the MCM is consistent with memory controller IO (or even the entire northbridge IO) being concentrated on that corner of the MCM.  I don't see any reason why it wouldn't all be on the same bus, with software addressing restrictions in place to reserve RAM for system services.  I wonder if they could be trying to pull another N64 low/high res thing with us, albeit with a firmware update this time.

Goodtwin, on 02 Apr 2013 - 06:47, said:Ok, so 32bit is the maximum bus for ram modules.  I was assuming that it would be higher since there are high bandwidth memories like GDDR5, but apprently they get the bandwidth by having lots and lots of ram modules on the memory bus, and they run at way higher speeds than DDR3.  So if a graphics card for example has a 256bit memory bus, it would have to have eight 32bit ram modules to get maximum bandwidth.  If they were to use 16bit ram modules on that same graphics card, then there would have to be 16 ram modules on that memory bus.  I had to go look at some PC GPU's to see how in the world they were getting all that bandwidth.  Even when looking at GDDR5 memory on Hynix website, your going to notice that the bandwidth per brick of ram isnt that impressive, which was strange to me at first, but then I realized that bandwidth is simply a result of having lots of ram chips.  So having more low density ram modules instead of fewer high density ram modules is actually beneficial for bandwidth. 

Yes. Thats what the channesl mean. a 64 bit bus has 2 channels in that case. For 'natural' 64 bit busses, its just as simple, more lanes connect to the different modules inside the chip. Its called a double wide, but its just 2 32 bit busses. After all, all ram chips are made of smaller modules under 1 housing. wii u has a 128 bit bus, in this case. with half sent to games and half to system.

Interleaving helps reduce some of the clutter, but its not always practical, the 360 didnt use it because it was just too hot already, so the ram only had half the bandwidth for the number of modules it had.

there are 4 modules for each ram chip pair on the wii u.

with 2 channels we have a 64 bit bus, technically a 128 bit bus, but half is cut off.

anand tech said all 4 added up to 1 64 bit bus.

If you are saying hynix says 32bit per brick (standard for ddr3 2 channel, 64 bit), we are looking at a doubling of the bandwidth from anandtech.

Notice how the pairs of ram are connected by bus lanes to the back ends?

actually, reminds me of the ps4 ram. That also had 'paired' pools.



Huh. only 8 lines per chip. Wii u has 3 more lanes per chip on its bus.

eh, for some reason the wii u pic disappeared.



it has 11 lanes to its bus per chip vs ps3's 8.

even with the lane split we see on the PS3 in that image, they were able to unlock more RAM for developers, by lowering the OS footprint.

[3Dude]

routerbad, on 02 Apr 2013 - 08:17, said:Just looked again at the Wii U motherboard.  The way the RAM bus lanes go into the MCM is consistent with memory controller IO (or even the entire northbridge IO) being concentrated on that corner of the MCM.  I don't see any reason why it wouldn't all be on the same bus, with software addressing restrictions in place to reserve RAM for system services.  I wonder if they could be trying to pull another N64 low/high res thing with us, albeit with a firmware update this time.

even with the lane split we see on the PS3 in that image, they were able to unlock more RAM for developers, by lowering the OS footprint.


I dont think this 12.8 GB coffin can fit any more nails in it.

[routerbad]

routerbad, on 02 Apr 2013 - 08:17, said:Just looked again at the Wii U motherboard.  The way the RAM bus lanes go into the MCM is consistent with memory controller IO (or even the entire northbridge IO) being concentrated on that corner of the MCM.  I don't see any reason why it wouldn't all be on the same bus, with software addressing restrictions in place to reserve RAM for system services.  I wonder if they could be trying to pull another N64 low/high res thing with us, albeit with a firmware update this time.

even with the lane split we see on the PS3 in that image, they were able to unlock more RAM for developers, by lowering the OS footprint.


I dont think this 12.8 GB coffin can fit any more nails in it.

No, I think not.  Something is seriously wrong with the Anand teardown, whether it was bias, not enough coffee that morning, or just someone who didn't understand what they were looking at.  It isn't that far of a stretch though, 10 years of tracing leads on motherboards and there is still a lot of mystery in their design for me.

 

When I first started building electronics every setting was a manual jumper setting, so you had to become familiar with where jumper leads were going and what they did.

[3Dude]

routerbad, on 02 Apr 2013 - 08:21, said:No, I think not.  Something is seriously wrong with the Anand teardown, whether it was bias, not enough coffee that morning, or just someone who didn't understand what they were looking at.  It isn't that far of a stretch though, 10 years of tracing leads on motherboards and there is still a lot of mystery in their design for me.
When I first started building electronics every setting was a manual jumper setting, so you had to become familiar with where jumper leads were going and what they did.


That 3 lanes wider per chip has got to be considered now too.

its typically 2 bits per line, ps3 had 8 per chip, for 4 16 bit busses that added up to 1 64 bit bus.

with 11 lanes x 2, thats 22 bit busses, x4 = an 88 bit bus.

That would put total peak bandwidth at 35.2 GB a second going into that north bridge.

Edited by 3Dude, 02 April 2013 - 02:30 PM.

[routerbad]

routerbad, on 02 Apr 2013 - 08:21, said:No, I think not.  Something is seriously wrong with the Anand teardown, whether it was bias, not enough coffee that morning, or just someone who didn't understand what they were looking at.  It isn't that far of a stretch though, 10 years of tracing leads on motherboards and there is still a lot of mystery in their design for me.
When I first started building electronics every setting was a manual jumper setting, so you had to become familiar with where jumper leads were going and what they did.


That 3 lanes wider per chip has got to be considered now too.

its typically 2 bits per line, ps3 had 8 per chip, for 4 16 bit busses that added up to 1 64 bit bus.

with 11 lanes x 2, thats 22 bit busses, x4 = an 88 bit bus.

That would put total peak bandwidth at 35.2 GB a second going into that north bridge.

I'm getting 61.6 GB/s, I think that would be overall for all four chips, I'm still assuming that they are all talking with one northbridge and memory controller, the bus clock multi is doubled.

[3Dude]

routerbad, on 02 Apr 2013 - 09:09, said:I'm getting 61.6 GB/s, I think that would be overall for all four chips, I'm still assuming that they are all talking with one northbridge and memory controller, the bus clock multi is doubled.

Ill be happy just with killing 12.8

Oh,

from the gpu die.



ddr3 io is the backwards L the chipworks word is on.

The whole shabangabang goes into the gpu along that corner

[routerbad]

routerbad, on 02 Apr 2013 - 09:09, said:I'm getting 61.6 GB/s, I think that would be overall for all four chips, I'm still assuming that they are all talking with one northbridge and memory controller, the bus clock multi is doubled.

Ill be happy just with killing 12.8

Oh,

from the gpu die.



ddr3 io is the backwards L the chipworks word is on.

The whole shabangabang goes into the gpu along that corner

Yeah that notion is pretty much dead and gone.  

 

That should be DDR3 IO from the memory controller if I'm not mistaken, unless the memory controller is on the GPU with CPU interconnects.

[3Dude]

routerbad, on 02 Apr 2013 - 09:34, said:Yeah that notion is pretty much dead and gone.  
That should be DDR3 IO from the memory controller if I'm not mistaken, unless the memory controller is on the GPU with CPU interconnects.


It could be. i have no idea though, as all i can see is the lanes head into that corner, the mcm heat spreader hides everything from view, and the next step we have is the gpu itself. We still havent seen that middle ground.

Edited by 3Dude, 02 April 2013 - 03:59 PM.

[routerbad]

routerbad, on 02 Apr 2013 - 09:34, said:Yeah that notion is pretty much dead and gone.  
That should be DDR3 IO from the memory controller if I'm not mistaken, unless the memory controller is on the GPU with CPU interconnects.


It could be. i have no idea though, as all i can see is the lanes head into that corner, the mcm heat spreader hides everything from view, and the next step we have is the gpu itself. We still havent seen that middle ground.

It does look to be headed straight into the GPU from the angle on the mobo.  

 

 

Yep, straight into the GPU, unless the memory controller and entire northbridge is sitting on the MCM just outside the GPU.

[3Dude]

routerbad, on 02 Apr 2013 - 10:17, said:It does look to be headed straight into the GPU from the angle on the mobo.  
gqSDvioKMCE2DKCr.huge_.jpg
Yep, straight into the GPU, unless the memory controller and entire northbridge is sitting on the MCM just outside the GPU.


Im guessing it goes straight to the gpu too.

The whole bandwidth, and then capacity is set aside. No halving bandwidths.

[routerbad]

routerbad, on 02 Apr 2013 - 10:17, said:It does look to be headed straight into the GPU from the angle on the mobo.  
gqSDvioKMCE2DKCr.huge_.jpg
Yep, straight into the GPU, unless the memory controller and entire northbridge is sitting on the MCM just outside the GPU.


Im guessing it goes straight to the gpu too.

The whole bandwidth, and then capacity is set aside. No halving bandwidths.

That amounts to an almost criminal oversight and underestimation of the memory performance.  No wonder developers were saying things along the lines of "we've gone way past that in terms of bandwidth, but I can't say any more than that."  I need to find the actual quote, its much better than memory serves.

[3Dude]

That amounts to an almost criminal oversight and underestimation of the memory performance.  No wonder developers were saying things along the lines of "we've gone way past that in terms of bandwidth, but I can't say any more than that."  I need to find the actual quote, its much better than memory serves.

I remember something along those lines from the nes article

[routerbad]

I remember something along those lines from the nes article

Thanks for that!

 

 

Not worth the geeky soap? (discussion with Wii U developers)

Even if this “bandwidth drama” is only debated within confined circles, it shouldn’t be discarded, especially to gauge the Wii U longevity in regard to technically demanding third-party titles. To better comprehend this situation, we had a little chat with a developer (wishing to remain anonymous), who has released a graphically solid retail game on Wii U.

InquiringMind: The first teardowns of the system happened, and it seems the 2GB of ram are DDR3-1600 chips on a 64 bit bus, up to 43% slower than the RAM bandwidth of Xbox360 & PS3.

Anonymous developer: These numbers are not the actual Wii U memory performance. I wonder if such low specs would even make a port from XBox360 possible.

Do you mean there is more to it, that the dismantling may have overlooked something and in fact the bandwidth is higher? Or perhaps those rates are indeed true, but your observations on the overall memory performance are better, thanks to the eDram and caches?

I’m not capable of calculating memory throughput of DRAM chips like those websites nor I know the memory controller or how many channels such a controller uses or the actual timings of those chips. But when using the Wii U CPU caches properly to write memory from A to B then these numbers above get exceeded by far. And I don’t mean theoretical throughput on paper but real throughput in a game situation.

But are you strictly talking of the 1GB of RAM or the whole memory chain, including the CPU caches that you’re referring to here or even the eDram? And if it’s the first case, could you not be aware of some kind of mechanism involving the caches and the eDram that would automatically speed up the data from or into the RAM, and that would explains your higher measured numbers?

I talked about the 1GB. But if our results differ from the theoretical limits i think we simply measure different things.

So if I understand right, you have a way to know the speed of the RAM at your end, and what you’ve seen is clearly greater than 12GB/S? Would you say it’s in the same ballpark than the 22GB/s bandwidth of the Xbox360?

In my experience the Wii U surpasses any of these numbers under the right conditions. But as said, i can’t calculate the theoretical bandwidth of such DRAM, I can only talk about the actual system memory performance which is very good for me.

 

So according to Anandtech, more of the same DRAM array on a faster bus with more lanes equals half the throughput, because Nintendo.

Edited by routerbad, 03 April 2013 - 09:51 AM.

[3Dude]

Thanks for that!
 
 
Not worth the geeky soap? (discussion with Wii U developers)
Even if this “bandwidth drama” is only debated within confined circles, it shouldn’t be discarded, especially to gauge the Wii U longevity in regard to technically demanding third-party titles. To better comprehend this situation, we had a little chat with a developer (wishing to remain anonymous), who has released a graphically solid retail game on Wii U.

InquiringMind: The first teardowns of the system happened, and it seems the 2GB of ram are DDR3-1600 chips on a 64 bit bus, up to 43% slower than the RAM bandwidth of Xbox360 & PS3.
Anonymous developer: These numbers are not the actual Wii U memory performance. I wonder if such low specs would even make a port from XBox360 possible.
Do you mean there is more to it, that the dismantling may have overlooked something and in fact the bandwidth is higher? Or perhaps those rates are indeed true, but your observations on the overall memory performance are better, thanks to the eDram and caches?
I’m not capable of calculating memory throughput of DRAM chips like those websites nor I know the memory controller or how many channels such a controller uses or the actual timings of those chips. But when using the Wii U CPU caches properly to write memory from A to B then these numbers above get exceeded by far. And I don’t mean theoretical throughput on paper but real throughput in a game situation.
But are you strictly talking of the 1GB of RAM or the whole memory chain, including the CPU caches that you’re referring to here or even the eDram? And if it’s the first case, could you not be aware of some kind of mechanism involving the caches and the eDram that would automatically speed up the data from or into the RAM, and that would explains your higher measured numbers?
I talked about the 1GB. But if our results differ from the theoretical limits i think we simply measure different things.
So if I understand right, you have a way to know the speed of the RAM at your end, and what you’ve seen is clearly greater than 12GB/S? Would you say it’s in the same ballpark than the 22GB/s bandwidth of the Xbox360?
In my experience the Wii U surpasses any of these numbers under the right conditions. But as said, i can’t calculate the theoretical bandwidth of such DRAM, I can only talk about the actual system memory performance which is very good for me.

 
So according to Anandtech, more of the same DRAM array on a faster bus with more lanes equals half the throughput, because Nintendo.

Also, everyone dismissed this because it came from nes.

[routerbad]

Also, everyone dismissed this because it came from nes.

Right, because only kotaku, anandtech, Digital Foundary have reliable sources and know what they are talking about...SMH

[Alex Atkin UK]

So what are we saying now then, potentially slightly under 4x the bandwidth of Xbox 360 (due to being clocked lower) as the Wii U might use 4 channels and likely at LEAST dual-channel?

 

I certainly have to agree that it would make little sense to have LESS bandwidth, and with the low-power architecture of the Wii U design overall I would be amazed if it wasn't at least dual-channel as its an almost free doubling of RAM bandwidth without drastically increasing the power/heat.