65 replies to this topic

[megafenix]

No, you have not.

1. You are using the standard operational frequency of the 476fp, and pairing it with the peak theoretical flops number. Doesnt work like that. You dont get peak theoretical flops unless you are running at max allowable frequency.

2. All of your bs applies perfectly well to customising the 750 to doing it instead of customizing the 476 to do broadway.

3. The documentation explicitely adresses those 'shortcomings' you are ranting about, further invalidating your frothing nonsense. You know, aside from the ones that were already flat out wrong.

 

 

so let me get this straight, is easier to modify the broadways cache controllers to support cache coherency for multicore, change the pipeline to support out of order, add L3 cache with edram and other stuff than just siply downclocking the 476fp and do some minor additional improvements?

 

sorry, but your statements make no sense, is easier to customize a 476fp since already packs all those things that broadway didnt have and is ore cost effective

 

Sorry, but you havent provided anything that proves the contrary,and not even marcan didnt address anything about flops or mhz but rather compatibility, which again i proved him wrong thanks to IBMs quotes about gekko FPU

Edited by megafenix, 03 December 2013 - 10:57 AM.

[3Dude]

so let me get this straight, is easier to modify the broadways cache controllers to support cache coherency for multicore, change the pipeline to support out of order, add L3 cache with edram and other stuff than just siply downclocking the 476fp and do additional improvements?
 
sorry, but your statements make no sense, is easier to customize a 476fp since already packs all those things that broadway didnt have and is ore cost effective

Sorry, but you havent provided anything that proves the contrary,and not even marcan addressed anything about flops or mhz but rather compatibility, which again i proved him wrong thanks to IBMs quotes about gekko

1. Its always been out of order.

2. Yes, those are pretty common place improvements architectures go through.

3. I like how you made a drawn out list for the 'showstopping' changes broadway would need to arrive at espresso (after hilariously posting that link to how nintendo had to make major changes in architecture to arrive at gekko)....

Yet merely write off the 476 customizations with a one liner 'some changes.

4. The burden of proof isnt on me, its on you, and you are failing spectacularly.

4. Marcan was specifically pointing out that only gekko and broadway have paired singles, because they were specific customizations nintendo asked for. STOP attempting whatever the hell you think is going on in your fake dimension where you thibk he claimed the opposite. Its getting painful to endure these gigantic foopahs you keep making.

[megafenix]

1. Its always been out of order.

2. Yes, those are pretty common place improvements architectures go through.

3. I like how you made a drawn out list for the 'showstopping' changes broadway would need to arrive at espresso (after hilariously posting that link to how nintendo had to make major changes in architecture to arrive at gekko)....

Yet merely write off the 476 customizations with a one liner 'some changes.

4. The burden of proof isnt on me, its on you, and you are failing spectacularly.

 

you sure about that?

well, why not ask IBM?

https://www-01.ibm.c...7256B72005C745C

 

 

"

1.12 Do any of the IBM 750XX processors support out of order transactions?

No. An excerpt from the 750CXe User Manual (section 8.2.2) explains this limitation.

In a pipelined implementation, data bus tenures are kept in strict order with respect to address tenures. However, external hardware can further decouple the address and data buses, allowing the data tenures to occur out of order with respect to the address tenures. This requires some form of system tag to associate the out-of-order data transaction with the proper originating address transaction (not defined for the 750CX/CXe interface). Individual bus requests and data bus grants from each processor can be used by the system to implement tags to support interprocessor, out-of-order transactions.

If your bridge chip/system controller supports out of order processing, do not enable this operation, as it can cause serious data integrity problems.

 

"

 

SUM THAT TO THIS ABOUT MULTICORE FOR 750

https://www-01.ibm.c...6B72005C745C#10

 

"

1.10 Can these processors be used in SMP designs?

750CXe/FX/GX (and other 750 processors) can work in an SMP environment; it just takes extra work in the software and OS kernel, and there will be extra bus traffic. The fundamental problem is that the cache management instructions (in particular dcbf, dcbst, dcbi) only operate on the local CPU's caches by default; they are not broadcast on the 60x bus for other processors to see unless ABE is set. Other SMP-capable PowerPC implementations broadcast these operations so they act on all caches in the system. In addition, the 750 family doesn't broadcast TLB invalidations, and it doesn't snoop instructions on the bus, so it wouldn't pick up these other operations even if they were broadcast.So using these processors in an SMP design would require having the software and OS ensure that each CPU in the system performed each of these tasks every time it needed to be done by one of the CPUs.

 

Basically, SMP operation can be done, but it will require a lot of software overhead, which may impact overall performance for both the kernel and user application code. As with other performance characteristics, it will depend heavily on the application.We have no quantitative data, but if two MEI processors are used without consideration to how tasks are partitioned between the processors, there will be a penalty due to shared data that will be continuously flushed out of one processor when the other processor needs it, along with the maintenance problems of tlbie and dcb operations. If tasks can be partitioned such that there is very little data sharing, then there will be correspondingly very little overhead for maintaining coherency between the two processors.

 

"

 

SO, WHO SHOULD I BELIEVE?

MARCAN OR IBM?

 

I WILL GO WITH IBM SICNE MARCAN HAS MADE TO MUCH VAGUE COMMENTS AND MANY OF THEM ARE SPECULATIONS

Edited by megafenix, 03 December 2013 - 11:24 AM.

[3Dude]

you sure about that?
well, why not ask IBM?
https://www-01.ibm.c...7256B72005C745C


"
1.12 Do any of the IBM 750XX processors support out of order transactions?
No. An excerpt from the 750CXe User Manual (section 8.2.2) explains this limitation.
In a pipelined implementation, data bus tenures are kept in strict order with respect to address tenures. However, external hardware can further decouple the address and data buses, allowing the data tenures to occur out of order with respect to the address tenures. This requires some form of system tag to associate the out-of-order data transaction with the proper originating address transaction (not defined for the 750CX/CXe interface). Individual bus requests and data bus grants from each processor can be used by the system to implement tags to support interprocessor, out-of-order transactions.
If your bridge chip/system controller supports out of order processing, do not enable this operation, as it can cause serious data integrity problems.

"

SUM THAT TO THIS ABOUT MULTICORE FOR 750
https://www-01.ibm.c...6B72005C745C#10

"
1.10 Can these processors be used in SMP designs?
750CXe/FX/GX (and other 750 processors) can work in an SMP environment; it just takes extra work in the software and OS kernel, and there will be extra bus traffic. The fundamental problem is that the cache management instructions (in particular dcbf, dcbst, dcbi) only operate on the local CPU's caches by default; they are not broadcast on the 60x bus for other processors to see unless ABE is set. Other SMP-capable PowerPC implementations broadcast these operations so they act on all caches in the system. In addition, the 750 family doesn't broadcast TLB invalidations, and it doesn't snoop instructions on the bus, so it wouldn't pick up these other operations even if they were broadcast.So using these processors in an SMP design would require having the software and OS ensure that each CPU in the system performed each of these tasks every time it needed to be done by one of the CPUs.
Basically, SMP operation can be done, but it will require a lot of software overhead, which may impact overall performance for both the kernel and user application code. As with other performance characteristics, it will depend heavily on the application.We have no quantitative data, but if two MEI processors are used without consideration to how tasks are partitioned between the processors, there will be a penalty due to shared data that will be continuously flushed out of one processor when the other processor needs it, along with the maintenance problems of tlbie and dcb operations. If tasks can be partitioned such that there is very little data sharing, then there will be correspondingly very little overhead for maintaining coherency between the two processors.

"

SO, WHO SHOULD I BELIEVE?
MARCAN OR IBM?

I WILL GO WITH IBM SICNE MARCAN HAS MADE TO MUCH VAGUE COMMENTS AND MANY OF THEM ARE SPECULATIONS

lmao. You have no idea what you are reading do you?

1. Nintendo owned specific custom hardware will not be included in that.

2. Nintendo specific 750's have enhancements to improve data transfer capability. Since you dont seem to understand, the difference between in order and out of order is the ability to transfer dependent data out until it is resolved, whilst moving in ready to go non dependant data.... Instead of just leaving it clogging the pipes until its resolved.

So I state again, both gekko and broadway, were actually already 'really' out of order, and a large improvement over stock 750's. Its almost like there is a reason every reference calls gekko and broadway out of order processors.

Including my broadway documentation.

[NintendoReport]

I'll make a fresh pot..

 

[megafenix]

lmao. You have no idea what you are reading do you?

1. Nintendo owned specific custom hardware will not be included in that.

2. Nintendo specific 750's have enhancements to improve data transfer capability. Since you dont seem to understand, the difference between in order and out of order is the ability to transfer dependent data out until it is resolved, whilst moving in ready to go non dependant data.... Instead of just leaving it clogging the pipes until its resolved.

So I state again, both gekko and broadway, were actually already 'really' out of order, and a large improvement over stock 750's. Its almost like there is a reason every reference calls gekko and broadway out of order processors.

Including my broadway documentation.

 

 

imao,  even the 750cl which was reported to be just a shrinked gekko at 90nm wit minor improvement didnt fully support out of order, you can go to the specs at ibm and clearly says that out of order is a lot limited to the point that transaction have to end in order

 

here

http://www.molecular...11/gamecube.pdf

 

"

PROJECT 4

Architecture Review of the Nintendo® GameCubeTM CPU

Ross P. Davis

CDA5155

Sec. 7233

08/06/2003

 

. Although execution can occur out-of-order, the completion unit will

complete instructions in-order to guarantee a consistent program state. As an aside, the out-of-order

execution is aided by reservation stations and register renaming, much like Tomasulo's algorithm.

 

"

 

sorry doc, but 476fp fully supports out of order, but 750 or gekko or broadway dont

 

here are 476fo documentations, very similar to what espresso supports

https://www-01.ibm.c..._04_07_2011.pdf

 

out of order

cache coherency for multicore

L3 cache edram

ddr3 memory controller

etc, etc

Edited by megafenix, 03 December 2013 - 11:40 AM.

[3Dude]

imao, even the 750cl which was reported to be just a shrinked gekko at 90nm didnt fully support out of order, you can go to the specs at ibm and clearly says that out of order is a lot limited to the point that transaction have to end in order

here
http://www.molecular...11/gamecube.pdf

"
PROJECT 4
Architecture Review of the Nintendo® GameCubeTM CPU
Ross P. Davis
CDA5155
Sec. 7233
08/06/2003

. Although execution can occur out-of-order, the completion unit will
complete instructions in-order to guarantee a consistent program state. As an aside, the out-of-order
execution is aided by reservation stations and register renaming, much like Tomasulo's algorithm.

"

sorry doc, but 476fp fully supports out of order, but 750 or gekko or broadway dont

1. 750cl has neither the gekko's. fpu improvements, nor data transfer improvements. Only nintendo custom processors in nintendo hardware have these. Making your already unnecessary grasping at straws, even more absurd.

2. Tomasulo's algorithm IS considered fully out of order. Obviously if you have exceptions that are waiting on dependent data, that are required by OTHER instructions, they are going to have to be done in order as they are data dependant on one another.

Getting those out of the way so non dependent instructions can be completed is the ENTIRE POINT of OoO, not proof its not OoO.

[megafenix]

1. 750cl has neither the gekko's. fpu improvements, nor data transfer improvements. Only nintendo custom processors in nintendo hardware have these. Making your already unnecessary grasping at straws, even more absurd.

2. Tomasulo's algorithm IS considered fully out of order. Obviously if you have exceptions that are waiting on dependent data, that are required by OTHER instructions, they are going to have to be done in order as they are data dependant on one another.

Getting those out of the way so non dependent instructions can be completed is the ENTIRE POINT of OoO, not proof its not OoO.

 

now who is speculating?

read carefully, its says similar to the algorithm not it, and also gekko transactions have to end " in order", a full out of order pipeline can end them in out of order

 

"

Although execution can occur out-of-order, the completion unit will

complete instructions in-order to guarantee a consistent program state. As an aside, the out-of-order

execution is aided by reservation stations and register renaming, much like Tomasulo's algorithm. When an

instruction is retired, the real register is updated with the rename register results. The description given in

the user manual sounds very similar to Tomasulo's algorithm, though the name “Tomasulo” is not

mentioned [223].

 

"

 

dont you find anything familiar with this?(read all please)

"

"
1.12 Do any of the IBM 750XX processors support out of order transactions?
No. An excerpt from the 750CXe User Manual (section 8.2.2) explains this limitation.
In a pipelined implementation, data bus tenures are kept in strict order with respect to address tenures. However, external hardware can further decouple the address and data buses, allowing the data tenures to occur out of order with respect to the address tenures. This requires some form of system tag to associate the out-of-order data transaction with the proper originating address transaction (not defined for the 750CX/CXe interface). Individual bus requests and data bus grants from each processor can be used by the system to implement tags to support interprocessor, out-of-order transactions.
If your bridge chip/system controller supports out of order processing, do not enable this operation, as it can cause serious data integrity problems.

"

 

In short, IBM says that out of order is possible in 750 but limited

 

the 750cl as the same problem, has no full out of order, 476fp is full out of order since the transactions both ocur in out of order and end in out of order

 

"

Edited by megafenix, 03 December 2013 - 12:08 PM.

[3Dude]

No, it doesnt genius, the 476fp is executed out of order, but completed in order, as specified in the documentation. Which I have.

Its right there on page 7 under the paragraph execution unit.

Good god you are a trip.

[megafenix]

3Dude, on 03 Dec 2013 - 08:11 AM, said:

No, it doesnt genius, the 476fp is executed out of order, but completed in order, as specified in the documentation. Which I have.

Its right there on page 7 under the paragraph execution unit.

Good god you are a trip.

well, genius, both have the same limitatation then, but there still the problem with the 750 that doesnt have cache coherency for multicore and also lacks ddr3 memory controller and l3 cache, not to mention that the 476fp is more suited for the Green Hills Software than the broadway or any 750

good god you are missing many points

look, this the advantage on green hills software i am pointing out
https://www-01.ibm.c.../4xx_6xx_an.pdf
"
Programming Model Differences of
the IBM PowerPC 400 Family and
600/700 Family Processors.


Abstract – This application note describes how the programming models differ between the IBM
400 family and the 600/700 family of PowerPC architecture processor implementations. It is
useful to system designers and programmers porting code from one family to another.
The 600/700 family is compliant with the original PowerPC processor architecture designed for
desktop applications.

The 400 family, designed for use in embedded environments, maintains
compatibility in the base User Instruction Set architecture. However, it defines separate Virtual
Environment and Operating Environment architectures that have been enhanced for embedded
applications. These optimizations have prompted changes in features such as memory
management, debug support, and cache access and control, and processor extendibility

"

 

 

 

 

 

remember this?
http://ghs.com/news/...tendo_WiiU.html
"

 

News & Press

Green Hills Software's MULTI Integrated Development Environment Selected by Nintendo for Wii U Development

Global Agreement Will Yield Richer Games, with Faster Time-to-Market
SAN JOSE, CA — March 27, 2012 — DESIGN West/ESC 2012, Booth #1227 —Green Hills Software, the largest independent vendor of embedded software solutions, has entered into a global license agreement that will enable Nintendo Co., Ltd. to provide Green Hills Software's MULTI® integrated development environment (IDE) to developers that are creating video game software for the upcoming Wii U platform, which is scheduled to be launched later this year.

 

 

"We selected the Green Hills Software solution because it generates highly optimized code, and Green Hills provides excellent global support," commented Mr. Genyo Takeda, senior managing director of Integrated Research & Design at Nintendo Co., Ltd.
"Green Hills Software has a long history of supplying the most demanding global corporations with the tools they need to build innovative yet cost-effective and reliable electronic products," commented Tim Reed, general manager of Advanced Products, Green Hills Software. "We are proud to be a valued partner of Nintendo."

About MULTI
The MULTI development environment supports more target processors, operating systems, and third-party tools than any other IDE—making it ideal for enterprise-wide deployment. Green Hills Software's MULTI integrated development environment includes the industry's most powerful and proven tools for developing embedded software with maximum reliability, maximum performance, and minimum code size. With the MULTI IDE's sophisticated capabilities, you can develop, debug, and optimize code more quickly, significantly reducing both development cost and time.

"

Edited by megafenix, 03 December 2013 - 01:27 PM.

[3Dude]

megafenix, on 03 Dec 2013 - 3:14 PM, said:
well, genius, both have the same limitatation then, but there still the problem with the 750 that doesnt have cache coherency for multicore and also lacks ddr3 memory controller and l3 cache, not to mention that the 476fp is more suited for the Green Hills Software than the broadway or any 750

good god you are missing many points

LMFAO wow that was quite the edit. I take it you found the documentation on your own. But how can yuo be sure its real? A megalomaniac bent on fooling everybody into belieiving the wii u's cpu is based on the 750 series and scouring the entire internet with doctored versions of ibm documentation!!!

Anyone noticing a pattern here? Eye of core (whoops, I mean Megafenix) Constantly flings out baseless nonsense, never has any proof whatsoever, demands everyone else show instant proof, or else his speculation is proven right, turns out to be completely wrong, is proven wrong, slightly retrofits his claims, until they have been proven so blatantly wrong, and each and every individual point is caught, nailed down, and eliminated to the point he possibly cant make anything else up... and then he changes the subject and brings in a fresh wall of nonsense he knows nothing about but is convinced is true.

Sigh, anyways...

Right... both 'Limited'... You realize there is a REASON its called out of order EXECUTION and not out of order GRADUATION (or, if better for you, out of order 'completions') Its a videogame systems cpu, exceptions dependencies and branches are what it eats for breakfast lunch and dinner- actually, you know what thats good enough for me. Yeah, they are both 'limited' the same.

Yeah.... those are actually pretty routine and standard upgrades to architecture, and in no way shape or form the immovable wall you are trying to make them out to be. Getting a 476 to emulate broadway/gekko would be a lot more difficult. In fact, the 400 series (which the 476 is the latest entry in) didnt even support cache coherency until the 440 entry.

Andd a 476 is a much, much poorer fit for a videogame console cpu than you think it is. You realize that the 476fp has no l2 or l3 cache right? You have to get a seperate companion core to even GET an l2 cache, and the l2 cache embedded onto espresso's cpu itself is 3x the size. Oh and that 3.6 mm^2 per core? Yeah, that doesnt count the companion core you need to get an l2 cache.

There is a TON of work that would need to go into the 476 fp, not even counting making it compatable with broadway/gekko. And really, its not that great of a chip compared core to core to an updated 750 thats been customized specifically for videogame performance. Probably why nintendo chose to enhance the 750 line instead of switch to the 476 line.

I mean, its not like they were looking for an i7 or something. The espresso, the enhanced custom tricore 750 looks to be very capable for what Nintendo wants out of the wii u.

*Looks at edit*


You are really serious arent you? You think you have like, found the golden terd salvation because you highlighted embedded systems dont you?

Heres a little problem with your information, its from back in 1999 when the ppc 750 was the g3 macintosh computers cpu, and the 400 series was a laughable little joke of a processor, thats only value was the fact it was incredibly tiny, as it was a horribly weak pos that couldnt even support multicore coherency.

See, in about the oh, I dont know DECADE and some change between now and then, the 750 series became embedded as well. In fact, thats its main purpose now Its embedded in printers, space craft, storage devices, routers, videogame systems.

Has been for a very, very long time.

[megafenix]

LMFAO wow that was quite the edit. I take it you found the documentation on your own. But how can yuo be sure its real? A megalomaniac bent on fooling everybody into belieiving the wii u's cpu is based on the 750 series and scouring the entire internet with doctored versions of ibm documentation!!!

Anyone noticing a pattern here? Eye of core (whoops, I mean Megafenix) Constantly flings out baseless nonsense, never has any proof whatsoever, demands everyone else show instant proof, or else his speculation is proven right, turns out to be completely wrong, is proven wrong, slightly retrofits his claims, until they have been proven so blatantly wrong, and each and every individual point is caught, nailed down, and eliminated to the point he possibly cant make anything else up... and then he changes the subject and brings in a fresh wall of nonsense he knows nothing about but is convinced is true.

Sigh, anyways...

Right... both 'Limited'... You realize there is a REASON its called out of order EXECUTION and not out of order GRADUATION (or, if better for you, out of order 'completions') Its a videogame systems cpu, exceptions dependencies and branches are what it eats for breakfast lunch and dinner- actually, you know what thats good enough for me. Yeah, they are both 'limited' the same.

Yeah.... those are actually pretty routine and standard upgrades to architecture, and in no way shape or form the immovable wall you are trying to make them out to be. Getting a 476 to emulate broadway/gekko would be a lot more difficult. In fact, the 400 series (which the 476 is the latest entry in) didnt even support cache coherency until the 440 entry.

Andd a 476 is a much, much poorer fit for a videogame console cpu than you think it is. You realize that the 476fp has no l2 or l3 cache right? You have to get a seperate companion core to even GET an l2 cache, and the l2 cache embedded onto espresso's cpu itself is 3x the size. Oh and that 3.6 mm^2 per core? Yeah, that doesnt count the companion core you need to get an l2 cache.

There is a TON of work that would need to go into the 476 fp, not even counting making it compatable with broadway/gekko. And really, its not that great of a chip compared core to core to an updated 750 thats been customized specifically for videogame performance. Probably why nintendo chose to enhance the 750 line instead of switch to the 476 line.

I mean, its not like they were looking for an i7 or something. The espresso, the enhanced custom tricore 750 looks to be very capable for what Nintendo wants out of the wii u.

*Looks at edit*


You are really serious arent you? You think you have like, found the golden terd salvation because you highlighted embedded systems dont you?

Heres a little problem with your information, its from back in 1999 when the ppc 750 was the g3 macintosh computers cpu, and the 400 series was a laughable little joke of a processor, thats only value was the fact it was incredibly tiny, as it was a horribly weak pos that couldnt even support multicore coherency.

See, in about the oh, I dont know DECADE and some change between now and then, the 750 series became embedded as well. In fact, thats its main purpose now Its embedded in printers, space craft, storage devices, routers, videogame systems.

Has been for a very, very long time.

 

 

well, try and find if current 750 support embdded and virtual environment architecture

 

oops, again not eyeofcore just megafenix, go check ign and nintendo enthusiast forums please

by the way, they way you defend marcan, are you marcan??

the one brakken said suffers of godcomplex??

      

      

 

                   

 

 

 

and in the meantime, try to see if you can get a real link to ibm espresso document and not a simple png that anyone can do with pdf editor and paint

 

is a custome processor, so we could even say it took things from the 476fp and the broadway like the fpu and ombined them dude, but saying is just a broadway is ridicuolus since lack smp support, lacks ddr3 memory controller, lacks l3 cache, etc

 

 

and i agree, has been many years but the 400 didnt stop in where it was either, it has also evolved and even more for embedded software solutions, and also was ready to support multicore`almost from the start while the 750 didnt, if onlty the 750 was based on the 604 but no it was based on the 603 so its performance on multicore wouldnt be so good, just look the bebox fro example and in any tech forum about processors anyone will tell you that 750 is bad choice for multicore and even IBM says so

 

i dont get your point about the 440, thats going back to 1999 and many things changed since then, where as for the 750 didnt get updated in the mesi or mersi protocol for cache coherency

 

 

wtill, quite interesting to note that IBM has stopped the production of new 750 processors since 2006 while the 400 processors still kept evolving like the 476fp that was announced in 2009 and also announced in the same plant that produced the broadway processor for wii

 

and 476fp is also suited for games, IBM says so, go check those pages correctly

http://www.datasheet...ASW0048131.html

 

"

The PowerPC 476FP476FP processor core is designed to meet the highend and low-end demands of multiple market applications. By maintaining the Power instruction set architecture (ISA), existing code for set top boxes, game consoles, communication devices, and other embedded applications can adopt this core and meet the current performance requirements of these applications. The core leverages an extensive PowerPC ecosystem providing ready solutions on which customers can build their applications.

 

The stability of the architecture ensures that, as applications grow, future derivatives can take advantage of the investment in an application code base, creating a model for reduced development spending. The ability to run multiple cores as part of an application allows the PowerPC 476FP 476FP processor core to scale from applications such as a uniprocessor mobile internet device to a network processor requiring multiple coherent cores on a single chip. Server Storage Networking Printer Set-top box/ Digital TV/ Games Automotive Aerospace/ Defense IBM PowerPC 476FP 476FP Embedded Processor Core Page 5 The PowerPC 476FP-a uniprocessor Peak performance · 1.6 GHz+ capability delivers peak performance for uniprocessor designs Exceptional scalability, supporting up to eight coherent processors on a single PLB6 arbiter 

 

"

Edited by megafenix, 03 December 2013 - 03:25 PM.

[3Dude]

Dude, you posted your own twitter feed as support for your argument. You have the same arguments, and the same obnoxious tenacity as last time. You do get bonus points for coming back to the same thread as gold is silver/the happening/wiiboy/cup of tea. Its like a frothing way too obsessed reality dodging nintendo fanboy reuinion thread. Like that one episode in every long running cartoon series where all the old villains come back at once in that team up? Yeah. Its like that.

Are you seriously asking for proof that the 7xx series can be used as an embedded microarchitecture? Seriously? Are you SERIOUSLY suggesting that the 7xx architecture is not capable of beingused in embedded computing systems? Do you not understand what an embedded computing system is? DUde, every freaking videogame console ever freaking made, has been an embedded system, with a freaking embedded cpu. DO you not understand what embedded software is? How its DIFFERENT than embedded hardware like an embedded cpu? Do you not understand that being BETTER for embedded software solutions means you are very very BAD for videogames????

http://en.wikipedia....bedded_software

This is NOT what you want the main computational processing unit on your videogame system to be doing!!!

Dude, you posted a document that was 15 years old. You are bragging about multi, when multi is just an integrated development environment for C, C++, EC++, and Ada. Game systems have had something similar but much much much much much much better and designed for, like for making games for a very long time. Its called a dev kit. the 400 series wasnt capable of multicore until a dual core 440 parallellized via 16 racks with over a thousand nodes per rack, was used for the super computer blue gene. The first 'normal'400 series to actually have been designed for multicore was the 460, which was in 2006, right before the 470 series. So NO, the 400 series was NEVER multicore from the beginning.

Oh my god, its like you have no comprehension of what you read, and you just pick out and bold words without understanding the meaning behind them. The things you are highlighting and underlinging, are so incredibly common place the fact you think you have found something here is... is... astounding.

You are like, literally a real life version of a cartoon character. Everything you say is completely wrong in this bizaare absurd way. Like, you have to TRY PURPOSEFULLY to fail this hard, because the law of averages dictates you should have accidentally gotten at least something right by now but you just.... Dont. Ever.

You just dont.

[grahamf]

This thread is getting out of hand.

[megafenix]

Dude, you posted your own twitter feed as support for your argument. You have the same arguments, and the same obnoxious tenacity as last time. You do get bonus points for coming back to the same thread as gold is silver/the happening/wiiboy/cup of tea. Its like a frothing way too obsessed reality dodging nintendo fanboy reuinion thread. Like that one episode in every long running cartoon series where all the old villains come back at once in that team up? Yeah. Its like that.

Are you seriously asking for proof that the 7xx series can be used as an embedded microarchitecture? Seriously? Are you SERIOUSLY suggesting that the 7xx architecture is not capable of beingused in embedded computing systems? Do you not understand what an embedded computing system is? DUde, every freaking videogame console ever freaking made, has been an embedded system, with a freaking embedded cpu. DO you not understand what embedded software is? How its DIFFERENT than embedded hardware like an embedded cpu? Do you not understand that being BETTER for embedded software solutions means you are very very BAD for videogames????

http://en.wikipedia....bedded_software

This is NOT what you want the main computational processing unit on your videogame system to be doing!!!

Dude, you posted a document that was 15 years old. You are bragging about multi, when multi is just an integrated development environment for C, C++, EC++, and Ada. Game systems have had something similar but much much much much much much better and designed for, like for making games for a very long time. Its called a dev kit. the 400 series wasnt capable of multicore until a dual core 440 parallellized via 16 racks with over a thousand nodes per rack, was used for the super computer blue gene. The first 'normal'400 series to actually have been designed for multicore was the 460, which was in 2006, right before the 470 series. So NO, the 400 series was NEVER multicore from the beginning.

You are like, literally a real life version of a cartoon character. Everything you say is completely wrong in this bizaare absurd way. Like, you have to TRY PURPOSEFULLY to fail this hard, because the law of averages dictates you should have accidentally gotten at least something right by now but you just.... Dont. Ever.

You just dont.

 

 

they can be used for embedded purposes, but wont give you the same performance like the 476fp that was designed for that in mind from the beginning

[NintendoReport]

[megafenix]

Dude, you posted your own twitter feed as support for your argument. You have the same arguments, and the same obnoxious tenacity as last time. You do get bonus points for coming back to the same thread as gold is silver/the happening/wiiboy/cup of tea. Its like a frothing way too obsessed reality dodging nintendo fanboy reuinion thread. Like that one episode in every long running cartoon series where all the old villains come back at once in that team up? Yeah. Its like that.

Are you seriously asking for proof that the 7xx series can be used as an embedded microarchitecture? Seriously? Are you SERIOUSLY suggesting that the 7xx architecture is not capable of beingused in embedded computing systems? Do you not understand what an embedded computing system is? DUde, every freaking videogame console ever freaking made, has been an embedded system, with a freaking embedded cpu. DO you not understand what embedded software is? How its DIFFERENT than embedded hardware like an embedded cpu? Do you not understand that being BETTER for embedded software solutions means you are very very BAD for videogames????

http://en.wikipedia....bedded_software

This is NOT what you want the main computational processing unit on your videogame system to be doing!!!

Dude, you posted a document that was 15 years old. You are bragging about multi, when multi is just an integrated development environment for C, C++, EC++, and Ada. Game systems have had something similar but much much much much much much better and designed for, like for making games for a very long time. Its called a dev kit. the 400 series wasnt capable of multicore until a dual core 440 parallellized via 16 racks with over a thousand nodes per rack, was used for the super computer blue gene. The first 'normal'400 series to actually have been designed for multicore was the 460, which was in 2006, right before the 470 series. So NO, the 400 series was NEVER multicore from the beginning.

You are like, literally a real life version of a cartoon character. Everything you say is completely wrong in this bizaare absurd way. Like, you have to TRY PURPOSEFULLY to fail this hard, because the law of averages dictates you should have accidentally gotten at least something right by now but you just.... Dont. Ever.

You just dont.

 

 

they can be used for embedded purposes, but wont give you the same performance like the 476fp that was designed for that in mind from the beginning

here is an example

http://www.freescale...note/AN1267.pdf

 

"

Application Note

PowerPC 603™ Hardware Interrupt Latency In

Embedded Applications

 

The PowerPC 603 microprocessor completes one instruction before recognizing an external interrupt. That one

instruction may cause exceptions such as an illegal operation exception, delaying the handling of the external

interrupt. We demonstrate that few of these instruction-caused exceptions occur in an embedded application

as compared to a general desktop computing environment.

 

In this paper, we examine the instruction flow, the interrupt recognition method, and interrupt latency factors of

the PowerPC 603 microprocessor. We show that the instruction-caused exceptions do not affect the interrupt

response of most embedded applications. We suggest ways system designers can minimize interrupt latency

for embedded applications. Finally, we describe how to use the PowerPC decrementer exception, as available

in the 603, to measure the hardware interrupt latency.

 

 

"

 

not just a 15 yea old document, but also one from 2009, 476fp has been optimized and has support for multicore and other things, 750 died a long time aago and ibm didnt have plans for fabrication at nodes lower than 90nm

 

seriously, at least the documents i provide are real, do you have one that at least has those credentials?

 

seriously, show me the full link form ibm to support marcans statements, because until now his statements about the paired singles and that 400 and 700 series are not compatible have been proven wrong

Edited by megafenix, 03 December 2013 - 03:35 PM.

[3Dude]

they can be used for embedded purposes, but wont give you the same performance like the 476fp that was designed for that in mind from the beginning

AN EMBEDDED SYSTEM IS NOTHING MORE THAN A CLOSED SYSTEM DEDICATED TO A SPECIFIC PURPOSE. IT HAS NOTHING TO DO WITH PROCESSOR POWER AND NO IMPACT ON PERFORMANCE, IT DOESNT HAVE ANY EDGE JUST BECAUSE IT WAS NEVER USED AS AN ACTUAL PROCESSOR FOR AN OPEN SYSTEM LIKE A PC YOU CRAZY CRAZY INDIVIDUAL.

The 400 series started out as embedded because it was far, far far far too weak to ever possibly hope to be commercially sold as a cpu for an open machine like a PC. It was used in tivo's and shredders, garbage compactors. It was for embedded systems.

You are so obnoxious an actual developer broke nda and risked his job to send a page of actual espresso documentation into the internet just to shut up your stupid nonsense and it doesnt even phase you!

[megafenix]

AN EMBEDDED SYSTEM IS NOTHING MORE THAN A CLOSED SYSTEM DEDICATED TO A SPECIFIC PURPOSE. IT HAS NOTHING TO DO WITH PROCESSOR POWER, IT DOESNT HAVE ANY EDGE BECAUSE IT WAS NEVER USED AS AN ACTUAL PROCESSOR FOR AN OPEN SYSTEM LIKE A PC YOU CRAZY CRAZY INDIVIDUAL.

The 400 series started out as embedded because it was far, far far far too weak to ever possibly hope to be commercially sold as a cpu for an open machine like a PC. It was used in tivo's and shredders, garbage compactors. It was an embedded system.

You are so obnoxious an actual developer broke nda and risked his job to send a page of actual espresso documentation into the internet just to shut up your stupid nonsense and it doesnt even phase you!

 

 

i know how it startded with 400 and also how went for the 750, but the facts are there

750 no cache coherency

750 no l3 cache with edram

750 no ddr3 memory controller

 

476fp cache coherency for multicore, both SMP and AMP

476fp l3 cache with edram

476fp ddr memory controller

476fp both for embedded and general purpose(you can clearly see that tehre are general purpose registers)

 

its not my fault things are like that

 

 

And i am not saying is a 476fp, just that could be based on it and add additional features and more power or whatever you want

doing it with the broadway would have been far more difficult, thats all what i am saying. why to do so if ibm already has done the hardwork with the 476fp? 

 

either way, it could be a mix of what the 476fp and broadway pack since the 476fp lacks the fpu capabilities it needs and well nintendo could have just take it from the broadway and put the fpu unit in the 476fp

 

this is what customization is about

not just put an old broadway and stick three of them together and expect them to work just like that, it doesnt work that way and the bebox was a good example of this

Edited by megafenix, 03 December 2013 - 04:00 PM.

[3Dude]

i know how it startded with 400 and also how went for the 750, but the facts are there
750 no cache coherency
750 no l3 cache with edram
750 no ddr3 memory controller
 
476fp cache coherency for multicore, both SMP and AMP
476fp l3 cache with edram
476fp ddr memory controller
476fp both for embedded and general purpose(you can clearly see that tehre are general purpose registers)
 
its not my fault things are like that
 
 
And i am not saying is a 476fp, just that could be based on it and add additional features and more power or whatever you want
doing it with the broadway would have been far more difficult, thats all what i am saying. why to do so if ibm already has done the hardwork with the 476fp? 
 
either way, it could be a mix of what the 476fp and broadway pack since the 476fp lacks the fpu capabilities it needs and well nintendo could have just take it from the broadway and put the fpu unit in the 476fp
 
this is what customization is about
not just put an old broadway and stick three of them together and expect them to work just like that, it doesnt work that way

No, No. No. No. Good god no. You cant just make crap up.

1. Marcan NEVER said the words you are putting in his mouth, he NEVER said the 476 and the 7xx series were incompatable. He said the gekko and the broadway, custom NINTENDO ONLY IMPROVED GAMING PROCESSOR BASED ON THE 750 LINE, was incompatable with the 476 series. Which is true, the gekko and the broadway are also incompatable with OTHER MEMBERS OF THE 750 LINE. They can run legacy 750 code, but other 750 processors CAN NOT RUN GEKKO OR BROADWAY PPC CODE BECAUSE THE OTHER 750 PROCESSORS DO NOT HAVE PAIRED SINGLES, and neither can or does the 476.

2. You dont understand what you are talking about. All newer processors in a series is compatable with older power processors code, Of the same series. Far, FAR less processors are cross series compatable, despite them all using power isa, the differences in architecture prevents it. This is moronically obvious, a processor with an altivec unit is obviously not going to be code compatable with a newer processor, WITHOUT an altivec unit.

3. No, the 476 would NOT be much much easier, it would be much much harder, because changing the entire architecture of the chip to be compatable with the customized nintendo specific architecture of the 750 series, with things like paired singles is faaaaaaaar more work than simply customizing the custom nintendo 750 to utilize modern technology unavailable in 1999, to support multicore.

4. Why do you keep insisting on a weaker cpu core than what is in the wii u? Seriously, you are looney toons.