270 replies to this topic

[Nollog]

It just struck me as strange a company like Nintendo would throw all their rams around the place and have them on a single bus.

I'm not good with maths though.

[3Dude]

MT41K256M16HA-125

Is the micron ram found in another teardown.

its wired 32 megs (mb of course) a pop by 16x 8 banks inside each 4gb chip.

So, good.



Also affixed on a 96 fgba, 10x 14mm in size, that samsung on its 84 fgba is looking completely like an odd man out.

huh.

Found a samsung dram brochure.

with that rams nomenclature with different specifications more in line with the others than that samsung ram overview page.

K4W4G1646B -HC(12/11/1A). 96-FBGA.

Edited by 3Dude, 05 April 2013 - 12:16 AM.

[NintendoReport]

MT41K256M16HA-125

Is the micron ram found in another teardown.

its wired 32 megs (mb of course) a pop by 16x 8 banks inside each 4gb chip.

So, good.



Also affixed on a 96 fgba, 10x 14mm in size, that samsung on its 84 fgba is looking completely like an odd man out.

huh.

Found a samsung dram brochure.

with that rams nomenclature with different specifications more in line with the others than that samsung ram overview page.

K4W4G1646B -HC(12/11/1A). 96-FBGA.

[routerbad]

MT41K256M16HA-125

Is the micron ram found in another teardown.

its wired 32 megs (mb of course) a pop by 16x 8 banks inside each 4gb chip.

So, good.



Also affixed on a 96 fgba, 10x 14mm in size, that samsung on its 84 fgba is looking completely like an odd man out.

huh.

Found a samsung dram brochure.

with that rams nomenclature with different specifications more in line with the others than that samsung ram overview page.

K4W4G1646B -HC(12/11/1A). 96-FBGA.

Could be a mis printed label.

[NintendoReport]

I appreciate you guys for continuing the research and calculations. 

[routerbad]

It just struck me as strange a company like Nintendo would throw all their rams around the place and have them on a single bus.

I'm not good with maths though.

But it is on a single bus.  That's what we were trying to disprove from the anandtech article, because that guy seems to believe that locking down to 1GB of RAM means that you are segregating the chips onto separate buses, each running at half speed.  Since we can show that all of the lanes from Mem2 are going directly into the GPU, we know that there is only one memory controller and everything is on one faster bus, which would allow it to benefit from bank and component interleave, as well as dual channel.

 

Then we went and showed that Anandtech's numbers were just..off. 

[Plutonas]

so thats the speed of wii u ram?  31.8 gb/s ?  or just for the ddr3... Because they said in the past that EDRAM boost that to 148gb/s... false?

 

An example is xbox720, it has 8gb ddr3 and 32mb of EDRAM...  its impossible for the ddr3 to be 170gb/s as they advertise it.

Edited by Plutonas, 05 April 2013 - 07:03 AM.

[3Dude]

MT41K256M16HA-125

Is the micron ram found in another teardown.

its wired 32 megs (mb of course) a pop by 16x 8 banks inside each 4gb chip.

So, good.



Also affixed on a 96 fgba, 10x 14mm in size, that samsung on its 84 fgba is looking completely like an odd man out.

huh.

Found a samsung dram brochure.

with that rams nomenclature with different specifications more in line with the others than that samsung ram overview page.

K4W4G1646B -HC(12/11/1A). 96-FBGA.

Hah. Somethings not sitting right with me again.

Im going back to counting lanes in the channels for now.

11 lanes= 22bit. (if it was 16 bit you would only count 8 'wires' coming from the ram chips)

so 800x2x4x22=140200/8=17.6 GB/s

Its already breaking the '16 bit bus' rule by having what appears to be a physical 22 bit bus.

And the bus looks wierd. Like, unnecessarily huge....

But im back to just feeling wierd about it.

But 17.6 Is an absolute. I can count the bus to get to that.

But i still think there is more to it.

Edited by 3Dude, 05 April 2013 - 07:10 AM.

[routerbad]

Hah. Somethings not sitting right with me again.

Im going back to counting lanes in the channels for now.

11 lanes= 22bit. (if it was 16 bit you would only count 8 'wires' coming from the ram chips)

so 800x2x4x22=140200/8=17.6 GB/s

Its already breaking the '16 bit bus' rule by having what appears to be a physical 22 bit bus.

And the bus looks wierd. Like, unnecessarily huge....

But im back to just feeling wierd about it.

But 17.6 Is an absolute. I can count the bus to get to that.

But i still think there is more to it.

They are really abnormally spaced and really fat.  Then there's the ten lanes to it's channel pair. 

[3Dude]

routerbad, on 05 Apr 2013 - 03:04, said:They are really abnormally spaced and really fat.  Then there's the ten lanes to it's channel pair. 


Yeah, even observing the timing twists doesnt account for how much space that bus takes up.

i dont think its a thermal consideration running at 1.5 volts and standard 800(1600)MHz. So whats the deal with that bus?

wonder what the memory controller is doing. .....
and memory multiplier at?

Edited by 3Dude, 06 April 2013 - 07:13 AM.

[Goodtwin]

The bus width is determined by the controller from a system point(x64, x32, etc..), but if your question is a DRAM point, the bus width is determined by DRAM(x4,x8,x16,x32). (Actually, the bus width term is used in system only. We use data width term in DRAM)
In H5TQ4G63MFR case, the max speed is 1866 Mb/se(each data pin).
The data width of H5TQ4G63MFR is x16(because it has 16 pins), so max bandwidth is 3.7GB/s. 
(Speed X Data Width = 1866Mb/s X 16pins X 1Byte/8bit(change to Byte)= 3732MB/s = 3.7GB/s)

 

Got this back from Hynix, took me quite a bit of back and forth with them to get the specific information that I was looking for, but here it is.  They make that chip in both a 800Mhz and 900Mhz chip, the Wii U ram chips are the 800Mhz chips, so the max bandwidth to that chip would be 3.2 GB/s like Anandtech said.   

 

I guess the 32 MB of edram really is allevitating the bandwidth issue.  There are a couple bits of information that support this, and the most prominent one being that the Gamecube/Wii took a similar approach. 

 

The 2MB Z-buffer/frame buffer is extremely helpful since we already know from our experimentation with HyperZ and deferred rendering architectures that Z-buffer accesses are very memory bandwidth intensive. This on-die Z-buffer completely removes all of those accesses from hogging the limited amount of main memory bandwidth the Flipper GPU is granted.

 

The Gamecube has 3MB of on GPU ram, 2MB for the Z-buffer and 1MB for texture cache. 

 

Describes predicated tiling in Xbox 360 development.

The Xbox 360 has 10 MB (10×1024×1024) of fast embedded dynamic RAM (EDRAM) that is dedicated for use as the back buffer, depth stencil buffer, and other render targets. Depending on the size and format of the render targets and the antialiasing level, it may not be possible to fit all targets in EDRAM at once. For example, 10 MB of EDRAM is enough to hold two 1280×720 32-bit surfaces with no multisample antialiasing (MSAA) or two 640×480 4× MSAA 32-bit surfaces. However, a 1280×720 2× MSAA 32-bits-per-pixel render target is 7,372,800 bytes. Combined with a 32-bit Z/stencil buffer of the same dimensions, it becomes apparent that 10 MB might not be sufficient.

 

The 360 had edram, but it was to small to be useful, making the 360 still very reliant on the main memory bandwidth.  So if the Wii U is able to write exclusively to the edram, then the 12.8GB/s of bandwdith is available for reading from the main memory, where as the 360 has a max read bandwidth of around 10GB/s.  This doesnt even take into account that the Wii U has enough edram to not only hold the framebuffer, but also cache some constantly used textures. 

 

In the end, we know the memory performance is good.  It has more memory and not a single developer is complaining about the performance.  I personally dont feel that developers have been able to completely leverage the strengths of the edram, but have a feeling Retro is going to show what the console is capable of in a couple of months.  Even Criterion was struggling to get Need For Speed Most Wanted running on Wii U well until Nintendo got them updated tools and information.  Its obvious that the way to get the best performance from the Wii U is very different from the 360, but even with a very limited amount of time with the updated tools and information, Criterion was able to pump out a finished product that performed best on Wii U.  Imagine what they could have accomplished with a full year of development on Wii U. 

[3Dude]

The problem is there are too many lanes.

If the memory was setup the way this specific information states, wed only have 8 'lanes'or wires leading out per ram chip.

We know what they said about data width, thats on the ram manufacturers end. Whats making the waves is the bus width, on system end. Its too big for a 16 bit bus per chip. Again, there would only be 8 wires per chip. (2 bits per wire).

Also, the edram is 3x the size of the 360's. That has to be filled by main. for example You can fill it up with more of the same quality textures, so you only have to dip into main less often, or with the same amount of textures, but of a higher quality. (or a combo). When you want to switch those out, you have to go to main at 12.8 GB/s

So, unless the 360 never came remotely close to its bandwith cap, a port of a 360 game with main bw of 22GB/s with higher res textures with main at 12.8GB/s still just doesnt seem possible. Sooner or later you have to read from main, which would bring things to a stutter... But it never does, it runs better.

Edited by 3Dude, 08 April 2013 - 08:32 AM.

[Goodtwin]

The problem is there are too many lanes.

If the memory was setup the way this specific information states, wed only have 8 'lanes'or wires leading out per ram chip.

 

I thought about that to, but when looking at the picture there are 11 lanes going to the outside of the chips, and then 10 lanes that connect each pair of chips.  Thats a total of 32 lanes for a pair of chips, 16 pins per chip, so it matches up with the number of pins in each ram module.   

[routerbad]

I thought about that to, but when looking at the picture there are 11 lanes going to the outside of the chips, and then 10 lanes that connect each pair of chips.  Thats a total of 32 lanes for a pair of chips, 16 pins per chip, so it matches up with the number of pins in each ram module.   

How so?  11 pins going straight to the GPU per chip, at 2bit per pin.  you are counting the ten lanes once for two chips, but on each chip there are between 21 and 23 lanes coming out, total pins per pair would be between 42 and 45, not 32.  At any rate, the share bus between each chip pair points to two separate interfaces (buses), otherwise they would all have lanes running to each other chip in a mesh pattern.

[3Dude]

I thought about that to, but when looking at the picture there are 11 lanes going to the outside of the chips, and then 10 lanes that connect each pair of chips. Thats a total of 32 lanes for a pair of chips, 16 pins per chip, so it matches up with the number of pins in each ram module.

In ddr, each lane gets 2 bits, one for the rise and fall of each frequency wavelength.



Thats why each chip of tgis 64bit gddr3 ram card has 8 lanes.

so, 8x2=16x4=64

Edited by 3Dude, 08 April 2013 - 08:55 AM.

[Goodtwin]

Hynix is giving you the maximum bandwidth per pin, and they are saying 1600Mb per pin and there are 16 pins, so 25,600Mb per chip, or 3.2GB/s.  Double Data is how you get 1600Mhz instead of 800Mhz.  800Mhz x 2 (double data) x 16bit.  The lanes is something that Nintendo would have to explain, its obviously different, but its still limited to the maximum bandwidth that of the chip. 

 

This isnt what I wanted to here either guys, but it is what it is.  Obviously its not an issue, as no developer has complained about memory performance, but the main memory bandwidth is 12.8GB/s. 

[3Dude]

Hynix is giving you the maximum bandwidth per pin, and they are saying 1600Mb per pin and there are 16 pins, so 25,600Mb per chip, or 3.2GB/s.  Double Data is how you get 1600Mhz instead of 800Mhz.  800Mhz x 2 (double data) x 16bit.  The lanes is something that Nintendo would have to explain, its obviously different, but its still limited to the maximum bandwidth that of the chip. 
 
This isnt what I wanted to here either guys, but it is what it is.  Obviously its not an issue, as no developer has complained about memory performance, but the main memory bandwidth is 12.8GB/s. 

It doesnt really double the clock speed, it simply sends 2 bits per lane per clock 'effectively doubling clock speed'

[routerbad]

Hynix is giving you the maximum bandwidth per pin, and they are saying 1600Mb per pin and there are 16 pins, so 25,600Mb per chip, or 3.2GB/s.  Double Data is how you get 1600Mhz instead of 800Mhz.  800Mhz x 2 (double data) x 16bit.  The lanes is something that Nintendo would have to explain, its obviously different, but its still limited to the maximum bandwidth that of the chip. 

 

This isnt what I wanted to here either guys, but it is what it is.  Obviously its not an issue, as no developer has complained about memory performance, but the main memory bandwidth is 12.8GB/s. 

If it was that low, developers would be talking about it, what we have heard from developers is if the max bandwidth from main is only 12.8GB/s they would not be able to port their game to the Wii U from the 360, or it would have to be scaled down texture wise.  

 

Also, we know how many pins are connected to the GPU from the DDR3 bus.  There are more pins being used than it should be able to according to hynix.  

[Goodtwin]

Thats why I am saying its not a problem.  The majority of bandwidth usage does not come from pulling assets from ram, but from the Z buffer, AA, framebuffer and so on.  This is all handled in the edram.  Like I said before, the 360 and PS3 could only read from the main ram at about 10GB/s, the Wii U would be able to do this all the time.  The Wii U may not ever have to write to the main memory, making the full use of the 12.8GB/s bandwidth. 

 

For me, the disscussion is over because I feel that Hynix gave me a concrete answer.  16 pins with 1600Mb per pin is an absolute.  You can hook that chip up to whatever controller you want, but the chip itself is limited.  Im not asking you guys to concede to this conclusion, if you want to continue to theorize different results thats cool, but I am comfortable with the research and conclusion that I have come to. 

 

Its been fun guys, I think we did an adimirable job digging for information on the subject, but feel that I am of the opinion that the hynix specs are absolute, while you guys still see it as subjective.  We all have plenty of information to make up our own minds, so it is what it is.  I am ready to move onto a new subject, so I will catch you guys in another thread.  Peace out fellas.

[3Dude]

Ots not as simple as that. We have two 'absolutes'

Ddr gives 2 bits per line, its what makes it ddr.

'In computing, a computer bus operating with
double data rate transfers data on both the
rising and falling edges of the clock signal . [1]
This is also known as double pumped , dual-
pumped , and double transition. The term
toggle mode is used in the context of NAND
flash memory .'

That means an 8 lane ddr bus is 16 bit.

its why all 64 bit gddr3 cards have 4 chips with 8 lanes.

Edited by 3Dude, 08 April 2013 - 09:53 AM.